Field of the Invention
The present invention relates to a pulse output circuit, a shift register and a display device. In this specification, it is defined that a display device includes a liquid crystal display device in which liquid crystal elements are used as pixels and a spontaneous luminous display device in which spontaneous luminous elements such as electro-luminescence (EL) elements are used. It is also defined that a drive circuit of the display device is a circuit for inputting an image signal into a pixel disposed in the display device to carry out a process of displaying an image and includes a pulse output circuit such as shift register and inverter and an amplification circuit such as amplifier.
Description of the Related Art
Recently, a display device in which a semiconductor thin film is formed on an insulating material, especially on a glass plate, particularly an active matrix type of display device using a thin film transistor (referred to as a TFT, hereinafter) has been popular. The active matrix type of display device using TFTs contains hundred thousands to millions of pixels arranged in the shape of a matrix and displays an image by controlling an electric charge of each pixel by means of a TFT disposed in each pixel.
Further, as a recent technology, there has been a technology developed, which relates to, other than a pixel TFT forming a pixel, a poly-silicon TFT in which a TFT is used in a peripheral area of a pixel portion to simultaneously form a drive circuit. This technology greatly contributes to downsizing and consumed power reducing of a device. Accordingly, a display device is an essential device to a display part of a mobile information terminal whose application field has been significantly increased recently.
A CMOS circuit, which is produced by combining an N-channel type of TFT and a P-channel type of TFT, is generally used as a circuit, which forms a drive circuit of a display device. Now a shift register will be described as an example of the CMOS circuit conventionally used in general. FIG. 11A illustrates an example of a shift register conventionally used and a part enclosed by a dotted line frame 1100 is a circuit for outputting one stage of pulses. In FIG. 11A, three stages of pulses are extracted to be shown. One stage of a circuit comprises clocked inverters 1101 and 1103 and an inverter 1102. A detailed structure of the circuit is shown in FIG. 11B. In FIG. 11B, the clocked inverter 1101 comprises TFTs 1104 to 1107; the inverter 1102 comprises TFTs 1108 and 1109; and the clocked inverter 1103 comprises TFTs 1110 to 1113.
The TFTs forming a circuit includes three electrodes of a gate electrode, a source electrode and a drain electrode. Generally, in the CMOS circuit, the N-channel type of TFT often uses a lower potential part as the source electrode and a higher potential part as the drain electrode, while the P-channel type of TFT often uses a higher potential part as the source electrode and a lower potential part as the drain electrode. Thus, one of the source electrode and the drain electrode is referred to as a first electrode and the other is referred to as a second electrode in order to prevent confusion in describing connection of TFTs in this specification.
An operation of the circuit will be now described. As for an operation of a TFT, a conductive condition where a channel is formed between impurity regions when potential is given to a gate electrode is referred to as ON, while a non-conductive condition where the channel between impurity regions are erased is referred to as OFF.
Refer to a timing chart shown in FIGS. 11A, 11B and 11C. A clock signal (referred to as a CK, hereinafter) and a clock reverse signal (referred to as a CKB, hereinafter) are respectively inputted to the TFTs 1107 and 1104. A start pulse (referred to as a SP, hereinafter) is inputted to the TFTs 1105 and 1106. When the CK is at an level H, the CKB is at a level L and the SP is at the level H, the TFTs 1106 and 1107 turn ON, an output at the level L is inputted into an inverter comprising the TFTs 1108 and 1109 and reversed to be outputted at the level H to an output node (SR out 1). Then, when the CK reaches the level L and the CKB reaches the level H while the SP is at the level H, a holding operation is taken in a loop comprising an inverter 1102 and a clocked inverter 1103. Thus, an output at the level H is continuously outputted to the output node. Next, when the CK reaches the level H and the CKB reaches the level L, a writing operation is taken in the clocked inverter 1101 again. An output at the level L is outputted to the output node since, the SP has already reached to the level L at that time. After this, when the CK reaches the level L and the CKB reaches the level H, the holding operation is taken again. The level L in the output node is held in the loop comprising the inverter 1102 and the clocked inverter 1103.
The above is an operation for one stage. Connection of the CK and the CKB is contrary in a subsequent stage, so that the polarity of the clock signal would be contrary to the above while an operation would be similar. The above is repeated alternately, and a sampling pulse is similarly outputted in order as shown in FIG. 11C thereafter.
A characteristic of a CMOS circuit is that it is possible to keep the consumed current down in the circuit as a whole since electric current flows only at a moment that logic is changed (from the level H to the level L, or from the level L to the level H) and does not flow while certain logic is held (although there is minute leak current in practice).